1. Field of the Invention
This invention relates to semiconductor chip packages, and more specifically to low-pin-count chip packages and manufacturing methods thereof.
2. Description of the Related Art
FIG. 1 is a low-pin-count chip package 100 according to a preferred embodiment disclosed in R. O. C. Publication No. 348306 entitled "Device Having Resin Package And Method Of Producing The Same". The low-pin-count chip package 100 includes a chip 110 sealed in a package body 120. The active surface of the chip 110 is provided with a plurality of bonding pads 110a electrically connected to a plurality of connection pads 130. The backside surface of the chip 110 is exposed from the package body 120 through a conductive adhesive layer 112. The connection pads 130 are located at the periphery of the chip 110 and exposed from the lower surface of the package body 120 for making external electrical connection.
R. O. C. Publication No. 348306 also discloses a method for making the low-pin-count chip package 100. The method mainly utilizes a metal frame 140 (see FIG. 2) to fabricate a plurality of the low-pin-count chip packages 100 simultaneously. The method comprises the steps of: (A) applying a photoresist layer over one surface of the metal frame 140, pattern transferring, and developing in a manner that areas on the metal frame 140 at which it is desired to form the connection pads 130 are not covered by the photoresist layer; (B) plating a layer of metal such as gold or palladium on the areas on the metal frame 140 without protection of the photoresist layer; (C) stripping the remaining photoresist; (D) attaching the backside surface of the semiconductor chip 110 onto the metal frame 140 through an adhesive layer; (E) electrically coupling the bonding pads 11Oa on the semiconductor chip 110 to the corresponding connection pads 130; (F) forming a package body over the semiconductor chip 110. Finally, a separation step is performed to remove the metal frame 140. As shown in FIG. 2, the separation step typically comprises selectively etching the metal frame 140 with the connection pads 130 remaining intact by an etching agent.
Since the package body 120 does not cover the exposed lower surface of the connection pads 130, it can not firmly lock the connection pads 130. Adhesion depends on the overall nature of the interface region. A method for promoting adhesion is increasing the area of the interface between the package body 120 and the connection pads 130. However, since the connection pads 130 are formed by plating, the thickness thereof is practically limited to the time for plating. Typically, thickness of the metal plating is only about 0.4 to 0.8 mil, which contributes quite little to the adhesion between the package body 120 and the connection pads 130.
The connection pads 130 are usually made of metal with good electrical conductivity such as copper but the package body 120 is made of insulating material such as epoxy molding compound. Accordingly, the bond between connection pads 130 and the package body 120 is relatively weak and the difference of the coefficient of thermal expansion (CTE) therebetween is very large. Because of the CTE mismatch, stresses are induced at the interface between the connection pads and the plastic package body as the conventional package experiences temperature cycling. The stresses, in turn, result in the delamination at the metal-plastic interface. When the delaminations had occurred at the plastic-metal interface, moistures from the environment are easy to penetrate into the plastic package body and accumulate in the delaminated area. Once moisture accumulates in the package, rapid temperature ramp-up will cause the moisture to vaporize and expand, thereby inducing an hygrothermal stresses in the delaminated area which causes the surrounding plastic package body to popcorn. One of the most common occurrence of package popcorning occurs when the package described above is surface-mounted to a printed wiring board during the Infra-Red reflowing process.
Therefore, there is a need for increasing the thickness of connection pads 130 so as to increase the area of the interface between the package body and the connection pads thereby promoting adhesion therebetween, thereby overcoming, or at least reducing the abovementioned problems of the prior art.
Further, the conventional package 100 is mounted to a substrate, such as a circuit board, like other leadless devices. For example, a PC board is screened printed with a solder paste in a pattern that corresponds to the pattern of the connection pads 130 exposed from the bottom surface of the package 100. The package 100 is then appropriately positioned on the PC board and the solder is reflowed. It should be understood that the exposed portions of the connection pads 130 of the package 100 can be printed with solder paste and then mounted to a substrate. However, either way requires extreme care in aligning the solder paste with the connection pads 130 exposed from the bottom surface of the package 100.
U.S. Pat. No. 5,900,676 discloses a low-pin-count chip package 150 (see FIG. 3) having a plurality of column leads 162. The package 150 comprises a semiconductor chip 172 disposed on a die pad 160 and electrically connected to the column leads 162. A package body 180 is formed over the semiconductor chip 172 and the column leads 162. The package 150 is characterized in that the die pad 160 and the column leads 162 extend outward from the package body 180. The projecting portions of the column leads 162 from the bottom of the package 150 facilitate surface mounting of the package 150 to a substrate.
U.S. Pat. No. 5,900,676 also discloses a method for making the low-pin-count chip package 150 comprising the steps of: (a) providing a copper foil having a polyimide layer 152 formed on the bottom surface thereof; (b) etching the copper foil so as to form a die pad 160 and a plurality of column leads 162 (see FIG. 4); (c) forming a metal layer 166 (such as gold or palladium) on the upper surface of the die pad 160 and column leads 162 as well as exposed areas on the surface of the polyimide layer 152 (see FIG. 5); (d) attaching a semiconductor chip 172 onto the metal layer on the die pad through an adhesive layer 170; (e) electrically coupling the bonding pads 172a on the semiconductor chip 172 to the corresponding column leads 162; (f) forming a package body 180 over the semiconductor chip 172, column leads 162 and the polyimide layer 152 (see FIG. 6); (g) removing the polyimide layer 152 and the metal layer 166 thereon simultaneously thereby obtaining the package 150.
U.S. Pat. No. 5,900,676 teaches that the metal layer 166 is formed by plating. Therefore, in step (c), the metal layer 166 should also appear on the side surfaces of the die pad 160 and the column leads 162 such that the die pad 160 and the column leads 162 will be removed from the package body 180 together with the polyimide layer 152 and the metal layer 166 during step (g). Accordingly, the side surfaces of the die pad 160 and the column leads 162 should be masked whereby the metal layer 166 will not form on the side surfaces thereof. However, this will introduce additional steps into the process for the package 150 thereby prolonging cycle time, and thereby increasing cost. Further, U.S. Pat. No. 5,900,676 also teaches that the thickness of the metal layer 166 is preferably half the thickness of the die pad 160 or the column leads 162. However, below a certain thickness, the die pad 160 and column leads 162 cannot be relied upon for providing adequate adhesion to the package body 180. Therefore, the time for plating the metal layer 166 will become so long that the cycle time is significantly increased. Thus, this previously described method for making the low-pin-count chip package 150 is quite not practical. Besides, in U.S. Pat. No. 5,900,676, the metal layer is preferable formed of noble metals such as gold or palladium, which means a high cost for the metal layer that is half as thick as the column leads.